The present invention relates to a semiconductor device having a multi-layer wiring structure made by a damascening process or a dual damascening process, and a method of manufacturing such a device.
An ultra-large scale integrated circuit (ULSI) employs a multilayer wiring structure in which wiring layers of three levels or more are formed.
FIGS. 1 and 2 show a semiconductor device prepared by a conventional wiring process. FIG. 2 is a cross sectional view taken along the line IIxe2x80x94II indicated in FIG. 1.
As can be seen in the figure, a field oxide layer 12 is formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.
On the semiconductor substrate 11, an insulating layer 15 is formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layer 15 from its surface to be through to the source-drain region 13. On the insulating layer 15, a first-level wiring layer having a plurality of wiring layers 17 is formed. Each of the plurality of wiring layers 17 is connected to the source-drain region 13 of the MOS transistor via the contact hole 16.
On the insulating layer 15, an insulating layer (interlayer dielectric) 18 is formed so as to completely cover the plurality of wiring layers 17. A contact hole 19 is made in the insulating layer 18 from its surface to be through to the plurality of wirings 17. On the insulating layer (interlayer dielectric) 18, a second-level wiring layer having a plurality of wiring layers 20 is formed. Each of the plurality of wiring layers 20 is connected to the wiring layers 17 of the first-level wiring layers via the contact hole 19.
On the insulating layer (interlayer dielectric) 18, a bonding pad 21 is formed. Further, on the insulating layer (interlayer dielectric) 18, an insulating layer (passivation dielectric) 22 is formed so as to completely cover the plurality of wiring layers 20 and the bonding pad 21. An opening 23 is made in the insulating film (passivation dielectric) 22 so as to expose the bonding pad 21.
In a semiconductor device manufactured by the conventional wiring process, a plurality of wirings 17 of the first-level wiring layer, a plurality of wirings 20 of the second-level wiring layer and the bonding pad 21 are formed by a photo engraving process (PEP), in which, a resist pattern is formed, and using the resist pattern as a mask, metal layers are etched by an anisotropic etching (such as RIE).
However, in an ULSI, the distance between wirings of the same level is becoming very narrow.
Therefore, the following drawbacks begin to arise.
First, it is very difficult to accurately pattern the wirings 17 and 20 of the wiring layers. This is because the resolution of the exposing device for forming resist patterns, cannot follow up wiring patterns which are becoming finer as the technology develops.
Second, it is very difficult to fill grooves resulting between wirings of the same level, with insulating layer, and therefore cavities are inevitably created between the wirings. This is because of a poor step coverage of the insulating layer. Such cavities adversely affect the multilayer wiring technique.
FIGS. 3 and 4 show a semiconductor device manufactured by a dual damascening process. FIG. 4 is a cross sectional view taken along the line IVxe2x80x94IV indicated in FIG. 3.
As can be seen in the figure, a field oxide layer 12 is. formed on a semiconductor substrate 11. In an element region surrounded by the field oxide layer 12, a MOS transistor having a source-drain region 13 and a gate electrode 14, is formed.
On the semiconductor substrate 11, insulating layers 15 and 24 are formed so as to completely cover the MOS transistor. A contact hole 16 is made in the insulating layers 15 and 24 from its surface to be through to the source-drain region 13.
The insulating layer 25 is formed on the insulating layer 24. In the insulating layer 25, a plurality of grooves 16b used for forming a first-level wiring layer, is formed. Bottom sections of the plurality of grooves 16b are made through to the contact hole 16a. 
A barrier metal 17a is formed on an inner surface of each of the contact hole 16a and the grooves 16. Further, on each of the barrier metals 17a, a metal (or metal alloy) portion 17b is formed so as to completely fill each of the contact hole 16a and the grooves 16b. The plurality of wirings which make the first level wiring layer, consist of the barrier metals 17a and the metal portions 17b. 
The surface of the insulating layer 25 meets with that of the first-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the first-level wiring layer, is connected to the source-drain region 13 of the MOS transistor.
On the insulating layer 25 and the first level wiring layer, the insulating layer (interlayer dielectric) 18 and the insulating layer 26 are formed. A contact hole 19a is formed in the insulating layers 18 and 26 from its surface to be through to the first-level wiring layer.
An insulating layer 27 is formed on the insulating film 26. A plurality of grooves 19b used for forming the second-level wiring layer, are formed in the insulating layer 27. Bottom sections of the plurality of grooves 19b are made through to the contact hole 19a. 
A barrier metal 20a is formed on an inner surface of each of the contact hole 19a and the grooves 19b. Further, on each of the barrier metals 20a, a metal (or metal alloy) portion 20b is formed so as to completely fill each of the contact hole 19a and the grooves 19b. The plurality of wirings which make the second level wiring layer, consist of the barrier metals 20a and the metal portions 20b. 
The surface of the insulating layer 27 meets with that of the second-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the second-level wiring layer, is connected to the first-level wiring layer.
In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad 21. The bonding pad 21 is made of a metal (or metal alloy), as in the case of the second-level wiring layer.
An insulating layer (passivation dielectric) 22 is formed on the insulation layer 27, the second-level wiring layer and the bonding pad 21. An opening 23 is made in the insulating layer 22 so as to expose the bonding pad 21.
Regarding the semiconductor device manufactured by the dual damascening process as described above, it is able to solve the drawbacks of the conventional wiring process, that is, the wiring pattern becoming out of focus when exposing, and the cavities resulting between wirings.
However, in the dual damascening process or damascening process, the chemical mechanical polishing (CMP) technique is employed. In the case where a bonding pad 21 is formed by the CMP technique, the central portion of the bonding pad 21 is excessively etched, resulting in dishing, that is, the bonding pad 21 is made into a dish-like shape.
FIG. 5 illustrates how dishing occurs.
More specifically, the CMP not only mechanically etch the metal layer 21xe2x80x2, but also chemically etch it. Therefore, in the case where the metal layer 21 (bonding pad) remains in a groove 19b which has a width sufficiently large as compared to its depth (note that the size of a bonding pad is usually about 100 xcexcmxc3x97100 xcexcm), the central portion of the metal layer 21 in the groove 19b is excessively etched mainly by chemical etching.
Such dishing easily causes a bonding error, that is, a wire cannot be bonded to the bonding pad 21 accurately during a wiring bonding operation, which results in the deterioration of the production yield.
The present invention has been proposed as a solution to the above-described drawback of the conventional technique, and the object thereof is as follows. That is, regarding the semiconductor device manufactured by the dual damascening process or damascening process, the bonding pad is formed to have a lattice shape, and the deformation of the lattice-shaped bonding pad is prevented so as to suppress bonding error, thereby improving the reliability and yield of the product.
In order to achieve the above-described object, there is provided, according to the present invention, a semiconductor device including: a bonding pad constituted by a conductive member filled in grooves made in an insulating layer having a flat surface; an etching stopper layer formed on the insulating layer and having an opening to expose the bonding pad; and a passivation layer formed on the etching stopper layer and having an opening to expose the bonding pad.
The grooves of the insulating layer are arranged in a lattice-like shape and the bonding pad has a lattice-like shape. The insulating layer and the passivation layer are made of silicon oxide, and the etching stopper layer is made of silicon nitride.
Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, in which a bonding pad is formed by making grooves in an insulating layer having a flat surface and filling the grooves with a conductive material, the method including the stops of: forming an etching stopper layer on the insulating layer and the bonding pad, the etching stopper layer being made of a material which can be etched selectively with respect to at least a material which is used to form the insulating layer; forming a passivation layer on the etching stopper layer, the passivation layer being made of a material which can be etched selectively with respect to at least the material used to form the etching stopper layer; removing only a portion of the passivation layer, which is situated above the bonding pad; and removing only a portion of the etching stopper layer, which is situated above the bonding pad.
The bonding pad is formed by forming a conductive material layer which completely covers the grooves on the insulating layer, followed by polishing the conductive material layer by the CMP. The passivation layer is etched by the RIE and the etching stopper layer is etched by the RIE or CDE.
As the grooves are filled with the conductive material, the bonding pad and the uppermost wiring layer are formed at the same time.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.